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features floating channel designed for bootstrap operation fully operational up to +200v tolerant to negative transient voltage, dv/dt immune gate drive supply range from 10v to 20v independent low and high side channels input logichin/lin active high undervoltage lockout for both channels 3.3v and 5v input logic compatible cmos schmitt-triggered inputs with pull-down matched propagation delay for both channels also available lead-free (pbf) packages high and low side driver product summary v offset 200v max. i o +/- 1.0a /1.0a typ. v out 10 - 20v t on/off 80 & 60 ns typ. delay matching 20 ns max. ir2011( s) & (pbf ) www.irf.com 1 typical connection (refer to lead assignments for correct configuration). this/these diagram(s) show electrical connections only. please refer to our application notes and designtips for proper circuit board layout. data sheet no.pd60217 revb applications audio class d amplifiers high power dc-dc smps converters other high frequency applications description the ir2011 is a high power, high speed power mosfet driver with independent high and low side referenced output channels, ideal for audio class d and dc-dc converter applications. logic inputs are compatible with standard cmos or lsttl output, down to 3.0v logic. the output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. propagation delays are matched to simplify use in high frequency applications. the floating channel can be used to drive an n-channel power mosfet in the high side configuration which operates up to 200 volts. propri- etary hvic and latch immune cmos technologies enable ruggedized monolithic con- struction. 8-lead soic ir2011s 200v to load v cc com lin hin v s v b ho hin com v cc lin lo 1 8 4 5 8-lead pdip ir2011
2 www.irf.com ir2011(s) & (pbf) absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage param- eters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. symbol definition min. max. units v b high side floating supply voltage -0.3 225 v s high side floating supply offset voltage v b - 25 v b + 0.3 v ho high side floating output voltage v s - 0.3 v b + 0.3 v cc low side fixed supply voltage -0.3 25 v lo low side output voltage -0.3 v cc +0.3 v in logic input voltage (hin & lin) -0.3 v cc +0.3 dv s /dt allowable offset supply voltage transient (figure 2) ? 50 v/ns p d package power dissipation @ t a +25 c (8-lead dip) ? 1.0 (8-lead soic) ? 0.625 r thja thermal resistance, junction to ambient (8-lead dip) ? 125 (8-lead soic) ? 200 t j junction temperature ? 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) ? 300 c/w w v c note 1: logic operational for v s of -4 to +200v. logic state held for v s of -4v to -v bs . symbol definition min. max. units v b high side floating supply absolute voltage v s + 10 v s + 20 v s high side floating supply offset voltage note 1 200 v ho high side floating output voltage v s v b v cc low side fixed supply voltage 10 20 v lo low side output voltage 0 v cc v in logic input voltage (hin & lin) com 5.5 t a ambient temperature -40 125 c recommended operating conditions for proper operation the device should be used within the recommended conditions. the v s and com offset ratings are tested with all supplies biased at 15v differential. v
www.irf.com 3 ir2011(s) & (pbf) symbol definition min. typ.max.unitstest conditions v ih logic ?1? input voltage 2.2 ? ? v il logic ?0? input voltage ? ? 0.7 v oh high level output voltage, v bias - v o ? ? 2.0 i o = 0a v ol low level output voltage, v o ? ? 0.2 20ma i lk offset supply leakage current ? ? 50 v b =v s = 200v i qbs quiescent v bs supply current ? 90 210 v in = 0v or 3.3v i qcc quiescent v cc supply current ? 140 230 v in = 0v or 3.3v i in+ logic ?1? input bias current ? 7.0 20 v in = 3.3v i in- logic ?0? input bias current ? ? 1.0 v in = 0v v bsuv+ v bs supply undervoltage positive going 8.2 9.0 9.8 threshold v bsuv- v bs supply undervoltage negative going 7.4 8.2 9.0 threshold v ccuv+ v cc supply undervoltage positive going 8.2 9.0 9.8 threshold v ccuv- v cc supply undervoltage negative going 7.4 8.2 9.0 threshold i o+ output high short circuit pulsed current ? 1.0 ? v o = 0v, pw 10 s i o- output low short circuit pulsed current ? 1.0 ? v o = 15v, pw 10 s v a v a static electrical characteristics v bias (v cc , v bs ) = 15v, and t a = 25 c unless otherwise specified. the v in , v th and i in parameters are referenced to com and are applicable to all logic input leads: hin and lin. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo. v cc = 10v - 20v dynamic electrical characteristics v bias (v cc , v bs ) = 15v, c l = 1000 pf, t a = 25 c unless otherwise specified. figure 1 shows the timing definitions. symbol definition min. typ.max.unitstest conditions t on turn-on propagation delay ? 80 ? v s = 0v t off turn-off propagation delay ? 75 ? v s = 200v t r turn-on rise time ? 35 50 t f turn-off fall time ? 20 35 dm1 turn-on delay matching | t on (h) - t on (l) | ? ? 20 dm2 turn-off delay matching | t off (h) - t off (l) | ? ? 20 ns
4 www.irf.com ir2011(s) & (pbf) functional block diagram lead definitions symboldescription 8-lead pdip 8-lead soic ir2011 ir2011s part number lead assignments hin logic input for high side gate driver output (ho), in phase lin logic input for low side gate driver output (lo), in phase v b high side floating supply ho high side gate drive output v s high side floating supply return v cc low side supply lo low side gate drive output com low side return v b lin uv detect delay v cc uv detect lo v s com s r uv q hin ho level shift circuit low voltage level shift 3v s-trigger 3v s-trigger high voltage buffer low voltage level shift v s v b ho hin com v cc lin lo 1 8 4 5 6 7 3 2 v s v b ho hin com v cc lin lo 1 8 4 5 6 7 3 2
www.irf.com 5 ir2011(s) & (pbf) figure 1. timing diagram 50% 50% 10% 90% 10% 90% 10% 90% hin / lin ho lo t rise t fall t on (h) t on (l) t off (h) t off (l) dm1 dm2
6 www.irf.com ir2011(s) & (pbf) 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) t u r n - o n p r o p a g a t i o n d e l a y ( n s ) typ. figure 2a. turn-on propagation delay vs. temperature 0 100 200 300 400 500 10 12 14 16 18 20 supply voltage (v) t u r n - o n p r o p a g a t i o n d e l a y ( n s ) figure 2b. turn-on propagation delay vs. supply voltage typ. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) t u r n - o f f p r o p a g a t i o n d e l a y ( n s ) typ. figure 3a. turn-off propagation delay vs. temperature 0 100 200 300 400 500 10 12 14 16 18 20 supply voltage (v) t u r n - o f f p r o p a g a t i o n d e l a y ( n s ) figure 3b. turn-off propagation delay vs. supply voltage typ.
www.irf.com 7 ir2011(s) & (pbf) 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature ( o c) t u r n - o n r i s e t i m e ( n s ) typ. max. figure 4a. turn-on rise time vs. temperature 0 20 40 60 80 100 10 12 14 16 18 20 supply voltage (v) t u r n - o n r i s e t i m e ( n s ) figure 4b. turn-on rise time vs. supply voltage typ. max. 0 10 20 30 40 50 -50 -25 0 25 50 75 100 125 temperature ( o c) t u r n - o f f f a l l t i m e ( n s ) typ. max. figure 5a. turn-off fall time vs. temperature 0 10 20 30 40 50 10 12 14 16 18 20 supply voltage (v) t u r n - o f f f a l l t i m e ( n s ) figure 5b. turn-off fall time vs. supply voltage typ. max.
8 www.irf.com ir2011(s) & (pbf) 0 10 20 30 40 50 -50 -25 0 25 50 75 100 125 temperature ( o c) d e l a y m a t c h i n g t i m e ( n s ) figure 6a. turn-on delay matching time vs. temperature typ. max. 0 10 20 30 40 50 10 12 14 16 18 20 supply voltage (v) d e a l y m a t c h i n g t i m e ( n s ) figure 6b. turn-on delay matching time vs. supply voltage typ. max. 0 10 20 30 40 50 -50 -25 0 25 50 75 100 125 temperature ( o c) d e l a y m a t c h i n g t i m e ( n s ) figure 7a. turn-off delay matching time vs. temperature typ. max. 0 10 20 30 40 50 10 12 14 16 18 20 supply voltage (v) d e a l y m a t c h i n g t i m e ( n s ) figure 7b. turn-off delay matching time vs. supply voltage typ. max.
www.irf.com 9 ir2011(s) & (pbf) 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 temperature ( o c) l o g i c " 1 " i n p u t v o l t a g e ( v ) min. figure 8a. logic "1" input voltage vs. temperature 0 1 2 3 4 5 10 12 14 16 18 20 supply voltage (v) l o g i c " 1 " i n p u t v o l t a g e ( v ) figure 8b. logic "1" input voltage vs. supply voltage min. 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 temperature ( o c) l o g i c " 0 " i n p u t v o l t a g e ( v ) max. figure 9a. logic "0" input voltage vs. temperature 0 1 2 3 4 5 10 12 14 16 18 20 supply voltage (v) l o g i c " 0 " i n p u t v o l t a g e ( v ) figure 9b. logic "0" input voltage vs. supply voltage max.
10 www.irf.com ir2011(s) & (pbf) 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 temperature ( o c) h i g h l e v e l o u t p u t ( v ) max. figure 10a. high level output vs.temperature 0 1 2 3 4 5 10 12 14 16 18 20 supply voltage (v) h i g h l e v e l o u t p u t ( v ) figure 10b. high level output vs. supply voltage max. 0.0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 temperature ( o c) l o w l e v e l o u t p u t ( v ) max. figure 11a. low level output vs. temperature 0.0 0.1 0.2 0.3 0.4 0.5 10 12 14 16 18 20 supply voltage (v) l o w l e v e l o u t p u t ( v ) figure 11b. low level output vs. supply voltage max.
www.irf.com 11 ir2011(s) & (pbf) 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) o f f s e t s u p p l y l e a k a g e c u r r e n t ( m a ) max. figure 12a. offset supply leakage current vs. temperature 0 100 200 300 400 500 50 80 110 140 170 200 v b boost voltage (v) o f f s e t s u p p l y l e a k a g e c u r r e n t ( m a ) max. 0 100 200 300 400 500 600 -50 -25 0 25 50 75 100 125 temperature ( o c) v b s s u p p l y c u r r e n t ( m a ) typ. max. 0 100 200 300 400 500 600 10 12 14 16 18 20 v bs floating supply voltage (v) v b s s u p p l y c u r r e n t ( m a ) typ. max.
12 www.irf.com ir2011(s) & (pbf) 0 100 200 300 400 500 600 -50 -25 0 25 50 75 100 125 temperature ( o c) v c c s u p p l y c u r r e n t ( m a ) figure 14a. v cc supply current vs. temperature typ. max. 0 100 200 300 400 500 600 10 12 14 16 18 20 v cc supply voltage (v) v c c s u p p l y c u r r e n t ( m a ) figure 14b. v cc supply current vs. v cc supply voltage typ. max. 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature ( o c) l o g i c " 1 " i n p u t b i a s c u r r e n t ( m a ) figure 15a. logic "1" input bias current vs. temperature typ. max. 0 20 40 60 80 100 10 12 14 16 18 20 supply voltage (v) l o g i c " 1 " i n p u t b i a s c u r r e n t ( m a ) typ. max.
www.irf.com 13 ir2011(s) & (pbf) 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 temperature ( o c) l o g i c " 0 " i n p u t b i a s c u r r e n t ( m a ) figure 16a. logic "0" input bias current vs. temperature max. 0 1 2 3 4 5 10 12 14 16 18 20 supply voltage (v) l o g i c " 0 " i n p u t b i a s c u r r e n t ( m a ) figure 16b. logic "0" input bias current vs. supply voltage max. 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v c c a n d v b s u v t h r e s h o l d ( + ) ( v ) min. figure 17. v cc and v bs undervoltage threshold (+) vs. temperature typ. max. 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v c c a n d v b s u v t h r e s h o l d ( - ) ( v ) min. figure 18. v cc and v bs undervoltage threshold (-) vs. temperature typ. max.
14 www.irf.com ir2011(s) & (pbf) 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 temperature ( o c) o u t p u t s o u r c e c u r r e n t ( a ) figure19a. output source current vs. temperature typ. 0 1 2 3 4 5 10 12 14 16 18 20 supply voltage (v) o u t p u t s o u r c e c u r r e n t ( a ) figure 19b. output source current vs. supply voltage typ. 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 temperature ( o c) o u t p u t s i n k c u r r e n t ( a ) figure 20a. output sink current vs. temperature typ. 0 1 2 3 4 5 10 12 14 16 18 20 supply voltage (v) o u t p u t s i n k c u r r e n t ( a ) figure 20b. output sink current vs. supply voltage typ.
www.irf.com 15 ir2011(s) & (pbf) -15 -12 -9 -6 -3 0 10 12 14 16 18 20 v bs floating supply voltage (v) m a x i m u m v s n e g a t i v e o f f s e t ( v ) figure 21. maximum v s negative offset vs. v bs floating supply voltage typ.
16 www.irf.com ir2011(s) & (pbf) 01-6014 01-3003 01 (ms-001ab) 8-lead pdip case outlines 01-6027 01-0021 11 (ms-012aa) 8-lead soic 8 7 5 6 5 d b e a e 6x h 0.25 [.010] a 6 4 3 1 2 4. outline conforms to jedec outline ms-012aa. notes: 1. dimensioning & tolerancing per asme y14.5m-1994. 2. controlling dimension: millimeter 3. dimensions are shown in millimeters [inches]. 7 k x 45 8x l 8x c y footprint 8x 0.72 [.028] 6.46 [.255] 3x 1.27 [.050] 8x 1.78 [.070] 4. outline conforms to jedec outline ms-012aa. 5 dimension does not include mold protrusions. 6 dimension does not include mold protrusions. mold protrusions not to exceed 0.25 [.010]. 7 dimension is the length of lead for soldering to a substrate. mold protrusions not to exceed 0.15 [.006]. 0.25 [.010] cab e1 a a1 8x b c 0.10 [.004] e1 d e y b a a1 h k l .189 .1497 0 .013 .050 basic .0532 .0040 .2284 .0099 .016 .1968 .1574 8 .020 .0688 .0098 .2440 .0196 .050 4.80 3.80 0.33 1.35 0.10 5.80 0.25 0.40 0 1.27 basic 5.00 4.00 0.51 1.75 0.25 6.20 0.50 1.27 min max millimeters inches min max dim 8 e c .0075 .0098 0.19 0.25 .025 basic 0.635 basic
www.irf.com 17 ir2011(s) & (pbf) order information basic part (non-lead free) 8-lead pdip ir2011 order ir2011 8-lead soic ir2011s order ir2011s leadfree part 8-lead pdip ir2011 order IR2011PBF 8-lead soic ir2011s order ir2011spbf this product has been designed and qualified for the industrial market. qualification standards can be found on ir?s web site http://www.irf.com/ . data and specifications subject to change without notice world headquarters: 233 kansas street, el segundo, california 90245 tel: (310) 252-7105 3/4/2008 leadfree part marking information lead free released non-lead free released part number date code irxxxxxx yww? ?xxxx pin 1 identifier ir logo lot code (prod mode - 4 digit spn code) assembly site code per scop 200-002 p ? marking code

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